An Implementation of 32 BIT CMOS Comparator in Mentor EDA Tools
Abstract: Comparison can be done with voltage level or current level in a given system using analog circuit of operational amplifiers but as digital interface became a common aspect of various systems since 1990s. CMOS logic dominates in bit wise comparison in any digital system and plays a vital role on many devices like Arithmetic Logic Unit (ALU), Microprocessor, Error detection, Digital Signal Processing (DSP) and Communication devices when two numbers are equal or which one is greater. In this paper a CMOS 32- bit comparator has been designed using Mentor tools. Comparator has two inputs, A and B. It produces three outputs, namely X,Yand Z. When A equals B the output X goes High or “1” a major process of equality check in any digital system. When A is greater than B, the output Y is “1” and when A is less than B, the output Z is “1”. Simulation and synthesis have performed using mentor graphics at 135nm technology.
Keywords: CMOS, Comparator, Mentor Tools, 135nm Technology
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A Comparison of 128 bit Addition Using Ripple Carry Adder with Carry Lookahead Adder in Mentor EDA Tools
Abstract: A complex process of adding two 128 bits has become a standard since 2018 as microprocessor have become to operate at 128 bits having a Tera byte by memory (1012) with over 1 GHz speed. There are two techniques that have been normally used so called Ripple Carry Adder and Carry Lookahead Adder. Using Mentor tools these two techniques will be explored and the results will be presented in simple fashion at 135 nm. But the technology has been rapidly moving from 135 nm to 90 nm to 65 nm.
Keywords: Addition, Ripple Carry Adder, Carry Lookahead Adder, Mentor Tools, 135nm Technology.
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A CMOS Design of 64 bit ALU using Mentor Tools
Abstract: Data processing has been driven by an Arithmetic Logic Unit, ALU in any computer. A four bit ALU began by Intel Corporation in 1971 in the design of 4004 microprocessor, first of kind. The basis of any logic gate is a transistor which can raise to a logic 1 or Logic 0 in less than 100 pico seconds (Ps) which translates 10 Giga Hertz, GHz. 16 Giga bit memory chip has been in production since 2012 but 64 bit microprocessor have been produced only at end of 2015 simple because of arithmetic operation and software development of course with cost. The time delay of a 64 bit operation of addition or subtraction may take twenty or fifty times more than a clock cycle and multiplication would take more than hundred clock cycles. So the design with reduction in area to make faster processing has been pushing semiconductor technology with 180 nano meter (nm) to 90 nm to 65 nm or even 45 nm but the cost or power or time to delivery has to evaluated. The Electronic Design Automation (EDA) tools have been heavily used to make front end design with netlist with rapid strides along backend design of layout with tape out also. This paper show the usage of Mentor EDA tools in the front design of 64 bit ALU at 130 nm technology with simulation.
Keywords: Arithmetic Logic Unit, Microprocessor, Giga Hertz, Electronic Design Automation and Mentor Tools.
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Performance Comparison of 64-Bit Adders
Abstract— The objective of this paper is to analyze and optimization of adders. Addition is essential operation in any digital, analog and control systems. Adders are part of not only arithmetic logic unit in computers but used in some other kind of processors too, where they are used to calculate addresses, table in dices , and similar operations for that we have to reduce the area. This paper mainly concentrated on the optimization of the area. As number of bits increase to add, the area would be increased to calculate the carry from each section. In this paper, we implemented the adders using mentor graphics tool. Simulation have done by Questa_sim and synthesis by Leonardo spectrum in 135nm technology.
Keywords— Questa_sim , Leonardo spectrum , mentor graphics, optimization, synthesis.
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Implementation of Telescopic Operational Transconductance Amplifier for using Bulk driven technique for Biomedical Applications
Abstract: Analog Design is focus on signal amplification,fidelity and filtering. This paper presents low noise,low power,high gain Two-stage Telescopic Operational Trans conductance Amplifier(OTA) for bio medical applications. OTA is a „voltage controlled current device‟.Proposed Two-stage Telescopic OTA is designed by using Bulk driven technique and push pull configuration. The designed OTA having an input voltage of 0.96V,DC gain of 91.2dB,slew rate of 125.6V/us, power dissipation of 5.9218mW. This design was done using 130nm Technology in Mentor Graphics Pyxis Tool and simulated in ELDO.
Keywords: OTA , bulk driven technique, push pull configuration,ELDO.
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Journal of Advanced Research in Dynamical and Control Systems
Abstract: UART is a structure, which is responsible for implementing Serial Communication Protocol. UART acts as the intercessor for Serial and parallel interfaces. Proposed design can be applied for serial communication over a computer accessories and input-output devices. This paper presents the design of UART to Bus interface and architecture. The UART design has programmable features for Parser, Baud Generator, Receiver and Transmitter. UART to bus IP verification is built here to find out whether the verification achieves the expected result or not. The entire RTL design is coded in Verilog. Simulation results are verified by using 130nm technology in Mentor graphics Questa sim tool.
Keywords: UART ,Baud Rate ,Parser, Verilog Implementation questa sim 10.4c.
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A Study of CMOS VLSI Technology Landscape Challenges towards 7 nm
Abstract: CMOS VLSI design has grown in complexity from a million transistor to billion in last 20 years from 1 um critical dimension to 10 nm and IBM brings a successful 7nm IC. Billions of mobiles and tablets besides servers have been the major product developments that pushed CMOS Technology year by year as predicted Gordon Moore, founder of Intel in 1968. Commercial electronic products have impacted in many years of industry as well as consumers. As mobile landscape dramatically changing India, new products will developed with CMOS Technology Node complexity, Advanced Lithography Process and Scale of Economics of IC manufacturing. Hardware revolution in India will be driven to new heights with advent of IOT, Cloud Computing and Big Data Analytics. This paper reviews the key CMOS Technology parameters that have driven IC Designs from Fabrication to product developments that bring return on investment with lower risk.
Keywords: CMOS, Technology, Lithograph, Semiconductor, Integrated Circuits
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